The present invention relates generally to semiconductor testing, and more particularly relates to techniques for obtaining improved accuracy and resolution from semiconductor test structures.
In order to facilitate the testing of integrated circuit (IC) devices, such as back-end-of-line (BEOL) testing, test structures are typically formed in the IC using a conventional semiconductor fabrication process. Traditionally, these BEOL test structures, for mechanical integrity tests as well as electromigration or stress-induced voiding tests, employ open-ended chains of alternating metal levels. The testing of BEOL test structures is generally limited by the number of available bond pads that can be tied to points on the physical structure.
Electromigration is the migration of metal ions (e.g., aluminum) in a conductor due to electrical current stress. At flux divergence sites, electromigration can give rise to voids and hillocks, which eventually can cause open or short circuit failure. Stress-induced voiding also can result in open circuit failure. In this case, however, the driving force is not the current but the high triaxial tensile stress in the encapsulated metal lines after processing. Both electromigration and stress-induced voiding are reliability degrading mechanisms that become more and more critical as dimensions reduce. Consequently, obtaining accurate testing data is a primary objective in order to improve the reliability of IC designs.
One problem with conventional testing methodologies, however, is that multiple failures deep within the BEOL test structure itself cannot be readily detected. For example, FIG. 1 illustrates a conventional thermal cycle test structure designed as a chain of alternating lower metal conductors 102 and upper metal conductors 104 connected by conductive vias 106 to examine the mechanical integrity between different levels of metal. Taps, namely, Tap1 and Tap2, to the test structure are made at the ends of the chain and, as such, an electrical test between the two taps will only indicate that an open circuit has occurred somewhere within the structure. However, details such as where the failure occurred or how many failures exist in the chain remain unknown. Additionally, the precise location of voiding is often not known unless a destructive failure analysis technique, such as, for example, electron beam induced current (EBIC), is employed.
There exists a need, therefore, in the field of semiconductor testing, for a nondestructive testing methodology that is capable of improving the accuracy and resolution of testing data obtained from semiconductor test structures.
The present invention provides techniques for obtaining improved accuracy and resolution from semiconductor test structures by removing the limit imposed by the number of bond pads associated with a semiconductor device. The invention, in one aspect, utilizes digital technology to allow taps on chain-type test structures at every link in the chain. In this manner, the testing methodology of the present invention is limited only by the number of bits available for addressing and/or the physical space available for the test structure.
In accordance with one embodiment of the invention, a semiconductor test circuit includes a plurality of at least first conductors and second conductors. The first and second conductors are operatively connected together by a plurality of conductive vias to form an open chain of alternating first and second conductors. A plurality of conductive taps are included, each of the taps being connected at a first end to a corresponding first conductor. The test circuit further includes a plurality of switching circuits, each of the switching circuits being operatively connected to a second end of a corresponding one of the conductive taps. Each of the switching circuits is configurable for selectively connecting the corresponding conductive tap to one of at least a first bus and a second bus in response to at least one control signal presented to the switching circuit, the first and second buses being connected to first and second bond pads, respectively.
In accordance with a preferred embodiment of the invention, the test circuit may further include a decoder operatively coupled to the switching circuits. The decoder is configurable to generate the at least one control signal for selectively accessing one or more of the plurality of first and second conductors in the chain. In this manner, the present invention advantageously increases the data resolution that may be obtained from the test structure for a given number of bond pads.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.